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 HD74ALVCH162827
20-bit Buffers / Drivers with 3-state Outputs
REJ03D0042-0400Z (Previous ADE-205-188B (Z) ) Rev.4.00 Oct.02.2003
Description
The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that e 10-bit buffer section are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.
Features
* * * * * * VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 12 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors external resistors are required. All outputs have equivalent 26 series resistors, so no ex
Rev.4.00, Oct.02.2003, page 1 of 9
HD74ALVCH162827
Function Table
Inputs OE1 L L H X H : High level L : Low level X : Immaterial Z : High impedance OE2 L L X H A L H X X L H Z Z Output Y
Rev.4.00, Oct.02.2003, page 2 of 9
HD74ALVCH162827
Pin Arrangement
1OE1 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 1Y5 8 1Y6 9 1Y7 10 GND 11 1Y8 12 1Y9 13 1Y10 14 2Y1 15 2Y2 16 2Y3 17 GND 18 2Y4 19 2Y5 20 2Y6 21 VCC 22 2Y7 23 2Y8 24 GND 25 2Y9 26 2Y10 27 2OE1 28
56 1OE2 55 1A1 54 1A2 53 GND 52 1A3 51 1A4 50 VCC 49 1A5 48 1A6 47 1A7 46 GND 45 1A8 44 1A9 43 1A10 42 2A1 41 2A2 40 2A3 39 GND 38 2A4 37 2A5 36 2A6 35 VCC 34 2A7 33 2A8 32 GND 31 2A9 30 2A10 29 2OE2
(Top view)
Rev.4.00, Oct.02.2003, page 3 of 9
HD74ALVCH162827
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage
*1, 2
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
Unit V V V mA mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation *3 at Ta = 55C (in still air) Storage temperature
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to e the device. These are stress ratings only, and functional operation of the device at these or any unctional other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO IOH Min 2.3 0 0 -- -- -- Low level output current IOL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -6 -8 -12 6 8 12 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.4.00, Oct.02.2003, page 4 of 9
HD74ALVCH162827
Logic Diagram
1OE1 1 1OE2 56 1A1
55 2
1Y1
To nine other channels
2OE1 28 2OE2 29 2A1
42 15
2Y1
To nine other channels
Rev.4.00, Oct.02.2003, page 5 of 9
HD74ALVCH162827
Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VCC (V) *1 VIH VIL Output voltage VOH 2.3 to 2.7 2.7 to 3.6 2.3 to 2.7 2.7 to 3.6 Min 1.7 2.0 -- -- Max -- -- 0.7 0.8 -- -- -- -- -- -- 0.2 0.4 0.55 0.55 0.6 0.8 5 -- -- -- -- 500 10 40 750 A A A A V IOH = -100 A IOH = -4 mA, VIH = 1.7 V IOH = -6 mA, VIH = 1.7 V IOH = -6 mA, VIH = 2.0 V IOH = -8 mA, VIH = 2.0 V IOH = -12 mA, VIH = 2.0 V IOL = 100 A IOL = 4 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.8 V IOL = 8 mA, VIL = 0.8 V IOL = 12 mA, VIL = 0.8 V VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V VOUT = VCC or GND VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at VCC or GND Unit V Test Conditions
Min to Max VCC-0.2 2.3 2.3 3.0 2.7 3.0 1.9 1.7 2.4 2.0 2.0
VOL
Min to Max -- 2.3 2.3 3.0 2.7 3.0 -- -- -- -- -- -- 45 -45 75 -75 -- -- -- --
Input current
IIN IIN (hold)
3.6 2.3 2.3 3.0 3.0 3.6
Off state output current
*2
IOZ ICC
3.6 3.6 3.0 to 3.6
Quiescent supply current ICC
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current.
Rev.4.00, Oct.02.2003, page 6 of 9
HD74ALVCH162827
Switching Characteristics
(Ta = -40 to 85C)
Item Propagation delay time Symbol tPLH tPHL Output enable time tZH tZL Output disable time tHZ tLZ Input capacitance CIN CO VCC (V) 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 3.3 3.3 Output capacitance 3.3 Min 1.0 1.0 1.2 1.0 1.9 1.3 Typ 3.5 6.0 7.0 Max 4.4 4.4 3.8 6.3 6.2 5.1 5.9 5.2 4.7 pF pF Control inputs Data inputs outputs ns OE Y ns OE Y Unit ns FROM (input) TO (output) A Y
Test Circuit
See under table 500 S1 OPEN
*1
GND 500
C L = 50 pF
Load Circuit for Outputs Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
OPEN GND 4.6 V
OPEN GND 6.0 V
Note:
1.
CL includes probe and jig capacitance.
Rev.4.00, Oct.02.2003, page 7 of 9
HD74ALVCH162827 Waveforms-1
tr 90 % Input 10 % t PLH Vref 90 % Vref 10 % t PHL tf VIH GND
VOH Output Vref Vref VOL
Waveforms-2
tf 90 % Vref 10 % t ZL Vref t ZH Waveform - B Vref t HZ VOH - 0.3 V 10 % t LZ tr 90 % Vref GND VOH1 Waveform - A VOL + 0.3 V VOL VOH VOL1 TEST VIH Vref VOH1 VOL1
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
VIH
Output Control
2.3 V 1.2 V 2.3 V GND
2.7 V 1.5 V 3.0 V GND
Notes:
1.
2. 3. 4.
All Notes: 1. ll input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , tr 2.0 ns, tf 2.0 ns. (VCC = 2.50.2 V) PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. (VCC = 2.7 V, 3.30.3 V) Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. The output are measured one at a time with one transition per measurement.
Rev.4.00, Oct.02.2003, page 8 of 9
HD74ALVCH162827
Package Dimensions
As of January, 2003
14.0 14.2 Max 56 29 6.10
Unit: mm
1 *0.19 0.05
0.50 0.08 M
28
1.0 8.10 0.20 0 - 8 *0.15 0.05 0.10 0.05 0.50 0.1
0.65 Max
1.20 Max
0.10
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-56DAV -- -- 0.23 g
Rev.4.00, Oct.02.2003, page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble alwa may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary placem circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is distrib therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). a 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life ci is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater aerosp use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. materials 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and ect cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. countr 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. therein
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